"Physical Design"

"Physical Design"

The physical layout is the procedure of remodeling a circuit description into the physical layout, which describes the placement of cells and routes for the interconnections among them.

ASIC Physical Design Flow:
The main steps in the ASIC physical design flow are:

• Design Netlist (after synthesis)
• Floorplanning
• Partitioning
• Placement
• Clock-tree Synthesis (CTS)
• Routing
• Physical Verification
• GDS II Generation

The physical layout is primarily based on a netlist that is the stop result of the Synthesis procedure. Synthesis converts the RTL layout normally coded in VHDL or Verilog HDL to gate-stage descriptions which the subsequent set of gear can study/understand. This netlist carries statistics at the cells used, their interconnections, the location used, and different information. Typical synthesis gear are

• Cadence RTL Compiler/Build Gates/Physically Knowledgeable Synthesis (PKS)
• Synopsys Design Compiler

During the synthesis process, constraints are applied to ensure that the design meets the required functionality and speed (specifications). Only after the netlist is verified for functionality and timing it is sent for the physical design flow.

Steps

FloorPlanning:

The first step inside the bodily design float is floorplanning. Floorplanning is the method of figuring out systems that should be positioned near together, and allocating area for them in this kind of manner as to fulfill the every now and then conflicting goals of to be had space (value of the chip), required overall performance, and the desire to have the whole thing near the whole lot else.

Based at the region of the layout and the hierarchy, a suitable floorplan is determined upon. Floorplanning takes into account the macros used in the layout, reminiscence, different IP cores and their placement desires, the routing possibilities, and additionally the region of the complete layout. Floorplanning also determines the IO shape and aspect ratio of the layout. A horrific floorplan will result in wastage of die area and routing congestion.

In many design methodologies, place and pace are the topics of trade-offs. This is because of limited routing resources, as the extra resources used, the slower the operation. Optimizing for the minimal area permits the design both to apply fewer assets and for greater proximity of the sections of the layout. This leads to shorter interconnect distances, fewer routing resources used, quicker quit-to-end sign paths, or even faster and more regular area and direction instances. Done efficaciously, there are no negatives to floorplanning.

As a widespread rule, information-route sections benefit most from the ground making plans, while random good judgment, country machines, and other non-dependent good judgment can thoroughly be left to the placer segment of the location and direction software.

Data paths are commonly the areas of the design wherein more than one bits are processed in parallel with every bit being changed the same way with perhaps some have an impact on from adjacent bits. Example systems that makeup records paths are Adders, Subtractors, Counters, Registers, and Muxes.

Partitioning:

Partitioning is a procedure of dividing the chip into small blocks. This is performed specifically to split special functional blocks and additionally to make placement and routing less complicated. Partitioning may be executed in the RTL layout segment when the design engineer walls the whole layout into sub-blocks and then proceeds to design each module. These modules are related collectively inside the major module known as the TOP LEVEL module. This kind of partitioning is commonly known as Logical Partitioning. It turned into the first step of the physical design cycle.

Placement:

Before the start of placement optimization, all Wire Load Models (WLM) are removed. Placement uses RC values from Virtual Router (VR) to calculate timing. VR is the shortest Manhattan distance between two pins. VR RCs are extra accurate than WLM RCs.

Placement is achieved in four optimization phases:

Pre-placement optimization

In placement optimization

Post Placement Optimization (PPO) earlier than clock tree synthesis (CTS)

PPO after CTS.

Pre-placement Optimization optimizes the netlist earlier than placement, HFNs (High Fanout Nets) are collapsed. It also can downsize the cells.

In-placement optimization re-optimizes good judgment based on VR. This can carry out mobile sizing, cellular transferring, mobile bypassing, net splitting, gate duplication, buffer insertion, location recuperation. Optimization performs a generation of setup fixing, incremental timing and congestion drove placement.

Post-placement optimization earlier than CTS performs netlist optimization with ideal clocks. It can restore setup, hold, max trans/cap violations. It can do placement optimization based on global routing. It redoes HFN synthesis.

Post-placement optimization after CTS optimizes timing with a propagated clock. It tries to keep clock skew.

Clock tree Synthesis:

The purpose of clock tree synthesis (CTS) is to reduce skew and insertion postpone. The clock is not propagated earlier than CTS as proven within the photograph. After CTS keep slack ought to enhance. Clock tree starts offevolved at. Sdc defined clock source and ends at stop pins of a flop. There are two sorts of forestall pins referred to as forget about pins and sync pins. 'Don't touch' circuits and pins in front cease (common sense synthesis) are dealt with as 'ignore' circuits or pins at back give up (physical synthesis). 'Ignore' pins are omitted for timing analysis. If the clock is split then separate skew evaluation is essential.

Global skew achieves 0 skews among synchronous pins without considering logic dating.

Local skew achieves zero skews among synchronous pins at the same time as considering common sense courting.

If a clock is skewed intentionally to improve setup slack then it is called beneficial skew.

Rigidity is the time period coined in Astro to indicate the rest of the constraints. Higher the pressure tighter is the limitations.

Clock After CTS

In clock tree optimization (CTO) clock may be shielded in order that noise is not coupled to other alerts. But protective will increase place via 12 to fifteen%. Since the clock signal is international in nature the same steel layer used for power routing is used for clock additionally. CTO is carried out by way of buffer sizing, gate sizing, buffer relocation, stage adjustment, and HFN synthesis. We attempt to enhance setup slack in pre-placement, in placement and publish placement optimization before CTS ranges while neglecting preserve slack. In post-placement optimization after CTS preserve slack is progressed. As an end result of CTS lot of buffers are delivered. Generally, for 100k gates, round 650 buffers are introduced.

Routing:

There are two styles of routing inside the bodily design process, international routing and specified routing. Global routing allocates routing assets which are used for connections. It additionally does a music project for a particular internet.

Detailed routing does real connections. Different constraints which are to be taken care for the duration of the routing are DRC, cord length, timing, and so forth.

Physical Verification:

Physical verification assessments the correctness of the generated format layout. This includes verifying that the format

Complies with all generation necessities – Design Rule Checking (DRC)

Is regular with the authentic netlist – Layout vs. Schematic (LVS)

Has no antenna consequences – Antenna Rule Checking

This additionally includes density verification at the entire chip stage...Cleaning density is a very vital step within the lower generation nodes

Complies with all-electric requirements – Electrical Rule Checking (ERC).